1. Field of the Invention
The present invention relates to the electrical testing of so-called RF integrated circuits comprising inputs and outputs designed to receive or deliver AC signals in the radiofrequency domain.
The present invention more particularly relates to the electrical testing of RF integrated circuits present on a silicon wafer before the wafer is sliced into individual components.
2. Description of the Prior Art
By way of an example, FIG. 1 shows a silicon wafer 1 on which a large number of integrated circuits 2 having the same structure have been made by photolithography. The magnified view of FIG. 2 shows an integrated circuit 2 with an active zone 3 and connection pads 4 electrically connected to the active zone 3. A greater magnification of the active zone 3 would reveal hundreds or even thousands of integrated circuits together forming various electronic functions that have to be tested.
Since the manufacturing yields for integrated circuits are below 100%, the electrical testing of the integrated circuits 2 that are still on the wafer 1 makes it possible to identify and reject defective integrated circuits or circuits lacking the expected characteristics, before the slicing of the wafer and the mounting of the individualized integrated circuits in a package or on an interconnection medium. This operation is therefore essential for reducing production costs, especially in the context of mass production.
FIG. 3 gives a schematic view of a conventional system for the testing of integrated circuits and wafers, comprising a test station 11 connected to a probe 12 by means of a harness of electrical cables 13. The probe 12 is a printed circuit card 14 provided with metal tips 15 arranged to coincide with the connection pads of an integrated circuit 2. The wafer 1 is positioned on a tray 16 that is mobile in the horizontal plane and the integrated circuits are tested one after the other by shift motions and rising and descending motions of the tray 16. The entire system is steered by a test program loaded into a memory 17 that determines the electrical characteristics of the test signal to be applied to the integrated circuits and the measurements to be made.
This conventional procedure for the testing of integrated circuits by means of a probe tip card, which is in widespread use in the industry, is nevertheless limited when it is sought to test RF integrated circuits comprising RF inputs/outputs requiring measurement frequencies ranging from some hundreds of MegaHertz to some GigaHertz. These are especially integrated circuits having analog modulation and demodulation functions, mixers, amplifiers, filters, voltage-controlled oscillators (VCOs), phase-locked loops (PLLs), etc. designed for radio receivers, television receivers, mobile radiotelephones, GPS receivers, etc. In this frequency domain, the electrical signals have short wavelengths and various phenomena of reflection and phase rotation appear in the probe 12 and in the conductors 13 connecting the probe to the test station 11. These phenomena of reflection and rotation distort the electrical measurements by creating interference and changes of electrical level. Furthermore, at high frequency, the copper tracks of the printed circuit card 14 and the probe tips 15 of the probe 12 have non-negligible parasitic capacitance and inductance.
To overcome these drawbacks, specialized firms have developed RF probes offering satisfactory characteristics at high frequency. In particular, the firm Cascade(trademark) Microtech in Oregon, 97005 USA, proposes RF probe tips (xe2x80x9ctransmission line probesxe2x80x9d) referenced xe2x80x9cAir Coplanarxe2x80x9d and RFIC membrane probe cards provided with microstrip HF conductors and contact bumps made of nickel. Probes of this kind offer a passband of several tens of Gigahertz, a low reflection coefficient S11 and a transmission coefficient S12 with an attenuation of less than 3 dB (see presentation of Cascade(trademark) products on http//www.cmicro.com).
At the same time, the manufacturers of measuring instruments such as the firm Teradyne(trademark) have developed test stations (the A580 series) having RF ports fitted out with an integrated network analyzer or vector network analyzer capable of determining the xe2x80x9cSxe2x80x9d parameters (S11, S12/S21 and S22) of a probe by the OSL (open, short, load) method. As is well known to those skilled in the art, the OSL method consists of the performance of three measurements by the successive application, to the output of the probe, of at least three standard loads, generally an infinite impedance (open circuit), a zero impedance (short circuit) and a 50 ohm impedance (load). On the basis of these three measurements, which are kept in the memory of the instrument, the vector network analyzer determines the xe2x80x9cSxe2x80x9d parameters of the probe, and the test station, during subsequent measurements, makes an automatic error correction designed to compensate for the influence of these parameters to obtain precise and reliable measurements. At present, the standard loads used are thin-layer circuits on ceramic substrate, calibrated by a national metrology laboratory.
The Applicant has however reached the conclusion that these various means for the electrical testing of RF integrated circuits do not enable the implementation of a satisfactory xe2x80x9con-linexe2x80x9d testing method.
Firstly, the Air Coplanar type RF transmission line probes require a manual setting of the orientation of tips and are reserved for laboratory measurements or small production outputs. The membrane probe cards provided with contact bumps, although they are specially designed for the testing of integrated circuits on wafers, require the use of standard circuits with specific high-cost thin layers in order to be calibrated. For various other practical reasons, the Applicant believes that the membrane probe cards are not appropriate for the mass production of integrated circuits where the numbers of units manufactured could amount to several millions.
Secondly, at each calibration, the tips or contact bumps of the probes are applied forcefully to the connection pads of the standard circuits, so as to break a surface layer of oxide that forms in contact with air and set up a good electrical contact (xe2x80x9ccold weldingxe2x80x9d). The thin-layer standard circuits, apart from their high cost price, are therefore subject to wear and tear and have short lifetimes.
Finally, the thin-layer standard circuits do not have the same thickness as silicon wafers and, in order to be installed, they require an adjusting of the tray 16 (FIG. 3) which is necessarily followed by another adjusting of the tray when the wafer is installed. This drawback is in addition to the fact that the RF probes require several calibration operations during the testing of a batch of chips. These various calibrations imply action by a qualified engineer and take up 5 to 10% of the time devoted to electrical testing.
Thus, a general goal of the present invention is to provide for a method for the calibration of an RF probe that is suited to mass production, and is economical and easy to implement while at the same time being precise and reliable and capable of being implemented, if necessary, by non-skilled staff.
A more particular goal of the present invention is to provide for a standard circuit that has a low cost price and simplifies the calibration of an RF integrated circuit probe.
This goal is achieved by providing for an elementary standard structure comprising at least two contact pads deposited on a silicon substrate by means of an electrically insulating layer, at least one standard load that is measurable from the contact pads and a conductive screen buried beneath the insulating layer.
According to the invention, a standard circuit is made, comprising a plurality of elementary standard structures having same type standard loads arranged so as to present contact pads corresponding by their location to RF connection pads of the integrated circuit to be tested.
According to one embodiment, the standard circuit comprises a remanent memory connected to contact pads corresponding, by their location, to non-RF connection pads of the integrated circuit to be tested.
According to the invention, there is also made a silicon wafer comprising a plurality of standard circuits according to the invention, or comprising both integrated circuits to be tested and standard circuits according to the invention.
The conductive screen present in each standard structure may be demarcated laterally by etching, or by trenches made in the substrate. According to one embodiment, one of the contact zones of an elementary standard structure is connected to the conductive screen. Furthermore, an elementary standard structure may comprise two standard loads in series, connected by their midpoint to the conductive screen. A standard structure may also comprise at least one contact pad enabling access to the midpoint of the two standard loads. A standard load may be an open circuit formed by two sections of conductive tracks that do not meet, a short-circuit between two sections of conductive tracks, a resistive element connecting two sections of conductive tracks, or again a capacitor comprising a conductive plate deposited on the insulating layer and overhanging the buried conductive screen.
To achieve homogeneity in the electrical characteristics of the standard circuits according to the invention and in the electrical characteristics of RF integrated circuits, the invention also provides for making RF integrated circuits comprising at least one conductive screen buried under two RF connection pads. As above, the conductive screen may be demarcated laterally by etching, or by trenches made in the substrate of the integrated circuit.
Therefore, in practice, a method according to the invention for the calibration of an RF integrated circuit test probe comprises a step for determining the characteristics of the RF transmission lines of the probe, carried out by means of a vector network analyzer and standard circuits according to the invention, present on a silicon wafer.
The present invention also relates to a method for the electrical testing of an RF integrated circuit present on a silicon wafer, by means of a test station provided with RF ports, a network analyzer and a probe, comprising a step for determining the RF characteristics of the probe, carried out by means of standard circuits according to the invention, present on a silicon wafer, the RF characteristics of the probe being used as corrective terms during the electrical testing of the integrated circuit.